Discover how digital circuits remember information. Watch clock signals trigger state changes in flip-flops, the fundamental building blocks of registers, counters, and computer memory.
| S | R | Q(t) | Q(t+1) |
|---|---|---|---|
| 0 | 0 | 0 | 0 (Hold) |
| 0 | 0 | 1 | 1 (Hold) |
| 0 | 1 | 0 | 0 (Reset) |
| 0 | 1 | 1 | 0 (Reset) |
| 1 | 0 | 0 | 1 (Set) |
| 1 | 0 | 1 | 1 (Set) |
| 1 | 1 | 0 | X (Invalid) |
| 1 | 1 | 1 | X (Invalid) |
The Set-Reset latch is the simplest memory element. Setting S=1 stores a 1 (sets Q=1), setting R=1 stores a 0 (resets Q=0). When both S and R are 0, the latch holds its previous state. S=1, R=1 is an invalid/forbidden condition that leads to an unpredictable state.
Used in debouncing circuits for mechanical switches, alarm systems (set by trigger, reset manually), and as building blocks for more complex flip-flops.
| Type | Inputs | Has Invalid? | Can Toggle? | Primary Use |
|---|---|---|---|---|
SR | S, R | Yes (S=R=1) | No | Basic storage |
D | D | No | No | Data registers |
JK | J, K | No | Yes | Versatile logic |
T | T | No | Yes | Counters |