Combinational Circuits

Explore circuits where the output depends only on the current inputs. Watch signals propagate through multiplexers, decoders, and adders -- the building blocks that route data and perform arithmetic in every processor.

Digital Logic FoundationsPrerequisite: Logic Gates

Scenarios:

2:1 Multiplexer

Gate Delay: 23 in / 1 out

2:1 MUXSelector

2 gate delays

AND + OR

SEL

Y: 0

Input Combo0 / 8

Gate Delay2

Prop. Steps0

Truth Table

8 rows

D0	D1	S	\|	Y
0	0	0	\|	0
1	0	0	\|	1
0	1	0	\|	0
1	1	0	\|	1
0	0	1	\|	0
1	0	1	\|	0
0	1	1	\|	1
1	1	1	\|	1

Signal Legend

High (1)

Low (0)

Inactive

Select

All Circuits

1.0x

Understanding the 2:1 Multiplexer

How It Works

A 2:1 multiplexer selects one of two data inputs (D0, D1) based on a single select line (S). When S=0, output equals D0. When S=1, output equals D1. It acts as a digital switch.

Current Computation

Inputs: D0=0, D1=0, S=0

Outputs: Y=0

Select lines choose input D0 = 0 as output

Real-World Applications

Used in data routing, bus selection, ALU operand selection, and memory address multiplexing. CPUs use multiplexers extensively to route data between registers and functional units.

Key InsightA 2:1 MUX can implement ANY single-variable Boolean function. The select line acts as the variable, and the data inputs define the function's output for each value. This is why FPGAs use MUX-based lookup tables.

Circuit Comparison

Circuit	Inputs	Outputs	Gate Delay	Category
2:1 MUX	3	1	2	Data Routing
4:1 MUX	6	1	3	Data Routing
2:4 DEC	3	4	2	Address Decoding
3:8 DEC	4	8	3	Address Decoding
Half Add	2	2	2	Arithmetic
Full Add	3	2	3	Arithmetic