Instruction Set Architecture

Explore MIPS instruction encoding and decoding. See how assembly instructions are translated into 32-bit binary machine code across R-type, I-type, and J-type formats.

Presets:

1.0x

Instruction Memory

Select a preset to load instructions

Assembly → Binary Encoding

Select a preset to begin encoding/decoding

Format Reference

RR-Type (Register)

Used for arithmetic and logical operations between registers. All operands come from registers.

opcode

6 bits

5 bits

shamt

5 bits

funct

6 bits

Examples: ADD, SUB, AND, OR, SLT, SLL, SRL

II-Type (Immediate)

Used for operations with a constant value, memory access (load/store), and conditional branches.

opcode

6 bits

5 bits

immediate

16 bits

Examples: ADDI, LW, SW, BEQ, BNE, SLTI

JJ-Type (Jump)

Used for unconditional jumps. Provides a 26-bit address field for the jump target.

opcode

6 bits

address

26 bits

Examples: J, JAL

Metrics

Instructions

0/0

Current Format

Active Field

Mode

Encode

Opcode (6 bits)

The operation code tells the CPU what type of instruction to execute. For R-type instructions, the opcode is always 000000 and the actual operation is determined by the funct field. For I-type and J-type, the opcode directly specifies the instruction.

MIPS has 32 registers ($0-$31), each addressed with 5 bits. rs is the first source register, rt is the second source (or destination in I-type), and rd is the destination register in R-type instructions.

Shift Amount (5 bits)

Used only by shift instructions (SLL, SRL) to specify how many bit positions to shift. For all other R-type instructions, this field is 00000.

Function Code (6 bits)

The funct field distinguishes between R-type operations. Since all R-type instructions share opcode 000000, this field specifies ADD (100000), SUB (100010), AND (100100), OR (100101), etc.

Immediate (16 bits)

I-type instructions include a 16-bit constant value. This can be a memory offset (for LW/SW), an arithmetic operand (ADDI), or a branch offset (BEQ/BNE). The value is sign-extended to 32 bits before use.

Jump Address (26 bits)

J-type instructions provide 26 bits for the target address. The full 32-bit address is formed by taking the upper 4 bits of PC+4 and appending the 26-bit address shifted left by 2 (word-aligned), giving a 256 MB jump range.

Key Concepts

*All MIPS instructions are exactly 32 bits (fixed-length encoding), simplifying fetch and decode hardware.
*The opcode is always in bits [31:26], allowing the control unit to quickly determine the format.
*R-type uses 3 register addresses + funct; I-type uses 2 registers + 16-bit immediate; J-type uses 26-bit address.
*ISA design balances instruction expressiveness against fixed-width encoding constraints.

Complete Encoding Table

Assembly	Format	Opcode	rs	rt	rd / imm / addr	funct	Binary (32-bit)
Load a preset to see the encoding table

MIPS Register Reference

$zero

#0 (00000)

Constant 0

$at

#1 (00001)

Assembler temp

$v0

#2 (00010)

Return value

$v1

#3 (00011)

Return value

$a0

#4 (00100)

Argument

$a1

#5 (00101)

Argument

$a2

#6 (00110)

Argument

$a3

#7 (00111)

Argument

$t0

#8 (01000)

Temporary

$t1

#9 (01001)

Temporary

$t2

#10 (01010)

Temporary

$t3

#11 (01011)

Temporary

$t4

#12 (01100)

Temporary

$t5

#13 (01101)

Temporary

$t6

#14 (01110)

Temporary

$t7

#15 (01111)

Temporary

$s0

#16 (10000)

Saved

$s1

#17 (10001)

Saved

$s2

#18 (10010)

Saved

$s3

#19 (10011)

Saved

$s4

#20 (10100)

Saved

$s5

#21 (10101)

Saved

$s6

#22 (10110)

Saved

$s7

#23 (10111)

Saved

$t8

#24 (11000)

Temporary

$t9

#25 (11001)

Temporary

$gp

#28 (11100)

Global ptr

$sp

#29 (11101)

Stack ptr

$fp

#30 (11110)

Frame ptr

$ra

#31 (11111)

Return addr

Supported Instruction Set

ADDR

ADD $t0, $t1, $t2

Add: $t0 = $t1 + $t2

00000001001010100100000000100000

SUBR

SUB $t0, $t1, $t2

Subtract: $t0 = $t1 - $t2

00000001001010100100000000100010

ANDR

AND $t0, $t1, $t2

Bitwise AND: $t0 = $t1 & $t2

00000001001010100100000000100100

ORR

OR $t0, $t1, $t2

Bitwise OR: $t0 = $t1 | $t2

00000001001010100100000000100101

SLTR

SLT $t0, $t1, $t2

Set on Less Than: $t0 = ($t1 < $t2) ? 1 : 0

00000001001010100100000000101010

SLLR

SLL $t0, $t1, 2

Shift Left Logical: $t0 = $t1 << 2

00000000000010010100000010000000

LWI

LW $t0, 4($t1)

Load Word: $t0 = Memory[$t1 + 4]

10001101001010000000000000000100

SWI

SW $t0, 8($t1)

Store Word: Memory[$t1 + 8] = $t0

10101101001010000000000000001000

ADDII

ADDI $t0, $t1, 10

Add Immediate: $t0 = $t1 + 10

00100001001010000000000000001010

BEQI

BEQ $t0, $t1, 3

Branch if Equal: if ($t0 == $t1) PC += 3 * 4

00010001000010010000000000000011

BNEI

BNE $t0, $t1, 5

Branch if Not Equal: if ($t0 != $t1) PC += 5 * 4

00010101000010010000000000000101

J 1024

Jump: PC = 1024

00001000000000000000010000000000

JALJ

JAL 2048

Jump and Link: $ra = PC + 4; PC = 2048

00001100000000000000100000000000