Single-Cycle Datapath
Visualize the complete MIPS single-cycle processor datapath. Watch data flow through PC, Instruction Memory, Register File, ALU, and Data Memory as each instruction executes in five phases: Fetch, Decode, Execute, Memory, and Write Back.
Read the instruction from Instruction Memory using the PC value. PC+4 is computed for next instruction.
Control unit generates signals from the opcode. Register file reads source registers rs and rt. Sign-extend produces 32-bit immediate.
ALU performs the operation. For R-type: arithmetic on register values. For I-type: add base + offset. For BEQ: subtract to check equality.
Data Memory is accessed. LW reads a word from the computed address. SW writes a word to memory. R-type instructions pass through.
Results are written back to the Register File. R-type writes ALU result. LW writes memory data. SW and BEQ do not write.
A register holding the memory address of the current instruction. Updated every cycle to PC+4 or branch target.
Read-only memory storing the program. Addressed by PC, outputs the 32-bit instruction word.
32 general-purpose 32-bit registers. Has two read ports (rs, rt) and one write port. Reads are combinational; writes occur on clock edge.
Arithmetic Logic Unit performs ADD, SUB, AND, OR, SLT. Outputs the result and a Zero flag for branch decisions.
Stores data values. Addressed by ALU result. MemRead enables load, MemWrite enables store operations.
Decodes the opcode field [31:26] and generates all control signals that orchestrate the datapath multiplexers and enables.
| Instruction | RegDst | ALUSrc | MemToReg | RegWrite | MemRead | MemWrite | Branch | ALUOp |
|---|---|---|---|---|---|---|---|---|
| R-type | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 10 |
| LW | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 00 |
| SW | X | 1 | X | 0 | 0 | 1 | 0 | 00 |
| BEQ | X | 0 | X | 0 | 0 | 0 | 1 | 01 |
- *In a single-cycle design, every instruction completes in one clock cycle. The clock period must be long enough for the slowest instruction (typically LW).
- *The critical path for LW goes through: PC, Instruction Memory, Register File, ALU, Data Memory, and back to Register File write.
- *MUXes are controlled by single-bit signals that select between two data sources (e.g., RegDst selects between rt and rd for the write register).
- *The single-cycle design is simple but inefficient: resources like the ALU sit idle during memory access. Pipelining solves this by overlapping instruction execution.