2.3
CPU Pipelining (5-Stage)
Watch instructions flow through IF ID EX MEM WB stages with hazard detection
1.0x
Presets:
Instruction Queue
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Hazards Detected
Start simulation to detect
Data Hazard: RAW dependency between instructions on same register.
Load-Use: LW followed by read of same register needs 1 stall even with forwarding.
Control: Branch evaluated in EX; instructions in IF/ID are flushed.
Clock Cycle
0
Completed
0
CPI
--
Stalls
0
Forwards
0
Current Pipeline State
IF
Instruction Fetch
empty
ID
Instruction Decode
empty
EX
Execute
empty
MEM
Memory Access
empty
WB
Write Back
empty
Pipeline Timing Diagram
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