2.5CPU Architecture
Cache Hierarchy Simulator
Visualize how CPU caches work with direct-mapped, set-associative, and fully associative organizations. Watch addresses decompose into tag, set index, and offset fields with hit/miss animations and LRU replacement.
Cache Organization
Cache Size:256 B
Block Size:16 B
Total Blocks:16
Sets:16
Ways:1
Tag Bits:8
Index Bits:4
Offset Bits:4
1.0x
Presets:
Memory Hierarchy
CPU--
L1 Cache1 cycle
L2 Cache10 cycles
Main Memory100 cycles
Address Decomposition
Start the simulation to see address decomposition.
Address Sequence
Choose a scenario preset.
Direct-Mapped: Each block maps to exactly one set. Fast but susceptible to conflict misses.
Set Associative: Multiple blocks per set reduces conflict misses. Uses LRU replacement.
Fully Associative: Any block can go anywhere. Most flexible but expensive to search.
Accesses
0
Hits
0
Misses
0
Hit Rate
0.0%
Miss Rate
0.0%
Avg Latency
--
Cache Contents(16 sets x 1 way)
| Set | Way 0 |
|---|---|
| [0] | empty |
| [1] | empty |
| [2] | empty |
| [3] | empty |
| [4] | empty |
| [5] | empty |
| [6] | empty |
| [7] | empty |
| [8] | empty |
| [9] | empty |
| [10] | empty |
| [11] | empty |
| [12] | empty |
| [13] | empty |
| [14] | empty |
| [15] | empty |
Running Hit Rate
Press Play or Step to begin
Access Trace
No accesses yet. Start the simulation.