2.6CPU Architecture
CPU Cache Simulator Advanced
Explore how loop patterns, array strides, and access order affect cache performance. Modify loop order, array size, and stride to see miss rate change in real time.
Cache Configuration
Access Pattern:
Speed1x
Accesses
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Hits
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Misses
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Hit Rate
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Sets
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Cache State
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Hit Rate Over Time
Start the simulation to see hit rate trends
Current Access
Press Play or Step to begin simulation.
Memory Array
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Current In Cache
Access Log
No accesses yet.
Sequential access achieves best hit rate due to spatial locality — each cache line fill serves multiple accesses.
Stride patterns skip elements, wasting loaded cache lines. Stride = line size means every access is a miss.
Row vs Column major shows why loop order matters for 2D arrays — row-major matches memory layout.