2.7CPU Architecture
Out-of-Order Execution Visualizer
Step through Tomasulo's algorithm with reservation stations and a reorder buffer. Watch instructions issue, execute out of order, and commit in order.
Scenarios:
Cycle 0
Speed1x
Instruction Pipeline
| # | Instruction | Issue | Exec Start | Exec End | WB | Commit | Stage |
|---|
Execution Timeline
Instruction
1
2
3
Issue
Execute
Write-Back
Commit
Reservation Stations
Reorder Buffer
Empty — no instructions issued yet.
Issue: Instructions enter reservation stations in order.
Execute: Instructions begin when operands are ready — out of program order.
Write-Back: Results broadcast to waiting stations via CDB.
Commit: Instructions retire from ROB in program order for precise exceptions.