2.8CPU Architecture
Virtual Memory & TLB Simulator
Visualize address translation from virtual to physical addresses through TLB lookup and page table walk. See page faults, TLB misses, and LRU replacement in action.
Scenarios:
Speed1x
Accesses
0
TLB Hits
0
TLB Hit Rate
0%
Page Faults
0
Fault Rate
0%
Translation Lookaside Buffer (4 entries)
TLB [0]
empty
TLB [1]
empty
TLB [2]
empty
TLB [3]
empty
Page Table (16 entries)
VPN 0
-
VPN 1
-
VPN 2
-
VPN 3
-
VPN 4
-
VPN 5
-
VPN 6
-
VPN 7
-
VPN 8
-
VPN 9
-
VPN 10
-
VPN 11
-
VPN 12
-
VPN 13
-
VPN 14
-
VPN 15
-
Physical Frames (8)
Frame 0
free
Frame 1
free
Frame 2
free
Frame 3
free
Frame 4
free
Frame 5
free
Frame 6
free
Frame 7
free
Address Sequence
TLB Hit PT Hit Page Fault
Access Log
No accesses yet.
TLB Hit: Fastest — address translated directly from TLB cache.
Page Table Hit: TLB miss but page is in memory — walk the page table.
Page Fault: Page not in memory — must load from disk (expensive!).