2.9CPU Architecture
Memory Ordering & Barriers Visualizer
See how CPUs reorder memory operations and how memory fences prevent it. Compare relaxed, TSO (x86), and sequential consistency models.
Memory Model
Scenarios:
Speed1x
CPU 1 might see Y=1 but X=0 (store reordering)
CPU 0 — Operations
Store Buffer
empty
CPU 1 — Operations
Store Buffer
empty
Shared Memory
X= 0
Y= 0
Relaxed (ARM/RISC-V): Any reordering is allowed. Requires explicit fences for ordering.
TSO (x86): Only store-load reordering allowed. Stores to different addresses can be seen in different orders by other CPUs.
Sequential Consistency: All operations appear in program order. Simplest to reason about, but most restrictive.